MIPS+汇编指令基础

1035MIPSAssemblyLanguage•Today,digitalcomputersarealmostexclusivelyprogrammedusinghigh-levelprogramminglanguages(PLs),e.g.,C,C++,Java•TheCPUfetch–executecycle,however,isnotpreparedtodirectlyexecutehigh-levelconstructslikeif-then-else,do-while,arithmetic,methodinvocations,etc.•Instead,aCPUcanexecutealimitednumberofratherprimitiveinstructions,itsmachinelanguageinstructionset–Machinelanguageinstructionsareencodedasbitpatternswhichareinterpretedduringtheinstructiondecodephase–AC/C++/Javacompilerisneededtotranslatehigh-levelconstructsintoaseriesofprimitivemachineinstructions104Whymachinelanguage?•Evenwithclevercompilersavailable,machinelanguagelevelprogrammingisstillofimportance:–machinelanguageprogramscanbecarefullytunedforspeed(e.g.,computationallyheavysimulations,controllinggraphicshardware)–thesizeofmachinelanguageprogramsisusuallysignificantlysmallerthanthesizeofhigh-levelPLcode–specificcomputerfeaturesmayonlybeavailableatthemachinelanguagelevel(e.g.,I/Oportaccessindevicedrivers)•Foranumberofsmallscalecomputers(embeddeddevices,wearablecomputers)–high-levelPLcompilersarenotavailableyet–orhigh-levelPLsaresimplynotadequatebecausecompilersintroduceuncertaintyaboutthetimecostofprograms(e.g.,brakecontrolinacar)105Machinelanguagevs.assemblylanguage•RealmachinelanguagelevelprogrammingmeanstohandlethebitencodingsofmachineinstructionsExample(MIPSCPU:addition$t0←$t0+$t1):1000010010100000000100000•Assemblylanguageintroducessymbolicnames(mnemonics)formachineinstructionsandmakesprogramminglesserror-prone:Example(MIPSCPU:addition$t0←$t0+$t1):add$t0,$t0,$t1•Anassemblertranslatesmnemonicsintomachineinstructions–Normally:mnemonic1:1←→machineinstruction–Also:theassemblersupportspseudoinstructionswhicharetranslatedintoseriesofmachineinstructions(mnemonic1:n←→machineinstruction)106TheMIPSR2000/R3000CPU•HerewewillusetheMIPSCPUfamilytoexploreassemblyprogramming–MIPSCPUoriginatedfromresearchprojectatStanford,mostsuccessfulandflexibleCPUdesignofthe1990s–MIPSCPUswerefoundinSGIgraphicsworkstations,WindowsCEhandhelds,CISCOrouters,andNintendo64videogameconsoles•MIPSCPUsfollowtheRISC(ReducedInstructionSetComputer)designprinciple:–limitedrepertoireofmachineinstructions–limitedarithmeticalcomplexitysupported–extensivesupplyofCPUregisters(reducememoryaccesses)•Here:workwithMIPSR2000instructionset(useMIPSR2000simulatorSPIM:~larus/spim.html)107MIPS:memorylayout•TheMIPSCPUisa32-bitarchitecture(allregistersare32bitswide)–Accessiblememoryrange:0x00000000–0xFFFFFFFF•MIPSisavon-Neumanncomputer:memoryholdsbothinstructions(text)anddata.–Specificmemorysegmentsarecoventionallyusedtotellinstructionsfromdata:AddressSegment0x7FFFFFFFstack↓↓↑↑0x10000000data0x00400000text0x00000000reserved–IfaprogramisloadedintoSPIM,its.textsegmentisautomaticallyplacedat0x00400000,its.datasegmentat0x10000000108MIPS:32-bit,littleendian•AMIPSwordhas32bits(ahalfword16bits,abyte8bits)•TheMIPSarchitectureislittle-endian:inmemory,aword(halfword)isstoredwithitsleastsignificantbytefirst–Example(representationof32-bitword0x11223344ataddressn):Addressnn+1n+2n+3Value0x440x330x220x11(IntelPentium:big-endian)•MIPSrequireswords(andhalfwords)tobestoredatalignedaddresses:–ifanobjectisofsizesbytes,itsstorageaddressneedstobedivisblebys(otherwise:CPUhaltswithaddresserrorexception)109MIPS:registers•MIPScomeswith32generalpurposeregistersnamed$0...$31Registersalsohavesymbolicnamesreflectingtheirconventional8use:RegisterAliasUsageRegisterAliasUsage$0$zeroconstant0$16$s0savedtemporary$1$atusedbyassembler$17$s1savedtemporary$2$v0functionresult$18$s2savedtemporary$3$v1functionresult$19$s3savedtemporary$4$a0argument1$20$s4savedtemporary$5$a1argument2$21$s5savedtemporary$6$a2argument3$22$s6savedtemporary$7$a3argument4$23$s7savedtemporary$8$t0unsavedtemporary$24$t8unsavedtemporary$9$t1unsavedtemporary$25$t9unsavedtemporary$10$t2unsavedtemporary$26$k0reservedforOSkernel$11$t3unsavedtemporary$27$k1reservedforOSkernel$12$t4unsavedtemporary$28$gppointertoglobaldata$13$t5unsavedtemporary$29$spstackpointer$14$t6unsavedtemporary$30$fpframepointer$15$t7unsavedtemporary$31$rareturnaddress8Mostoftheseconventionsconcernprocedurecallandreturn(libraryinteroperability)110MIPS:loadandstore•TypicalfortheRISCdesign,MIPSisaload-storearchitecture:–Memoryisaccessedonlybyexplicitloadandstoreinstructions–Computation(e.g.,arithmetics)readsoperandsfromregistersandwritesresultsbackintoregisters•MIPS:loadword/halfword/byteataddressaintotargetregisterr(r←(a)):InstructionRemarkPseudo?lwr,alhr,asignextensionlbr,asignextensionlhur,anosignextensionlbur,anosignextension111MIPS:loadandstore•Example(loadword/halfword/byteintotemporaryregisters):.text.globl__start__start:#loadwithsignextensionlw$t0,memorylh$t1,memorylb$t2,memory#loadwithoutsignextensionlhu$t3,memorylbu$t4,memory.datamemory:.word0xABCDE080#littleendian:80E0CDABRegisterValue$t00xABCDE080$t10xFFFFE080$t20xFFFFFF80$t30x0000E080$t40x00000080112MIPS:loadandstore•MIPS:storeword/halfword/byteinregisterrataddressa(a←r):InstructionRemarkPseudo?swr,ashr,astoresl