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1Cortex-M–TheStandardArchitectureforMCUApplicationsAndyLuoEmbeddedMarketingManagerAndy.luo@arm.com2MarketChallenges8/16-bitrunningoutofperformanceheadroomAscomplexityrisessodoesfrequencyandmemoryrequirementMorefeaturesatlowercostIncreasingconnectivity(e.g.USB,Ethernet,802.15,NFC)DriveforbettercodereuseAnalogdeviceswithincreasingprocessingandcommunicationEnergyefficiencyWirelesssensors,motorcontrol,metering3MarketMigrationto32-bitGatheringMomentumAlgorithm complexity increasingIntegration of multiple functionality into single processing subsystem“Black box” systems starting to include networking connectivityEnergy efficiency becoming increasingly importantAssembler programming replaced with C4ARMCortex-ASeries:Applicationsprocessorsforfeature-richOSanduserapplicationsARMCortex-RSeries:Embeddedprocessorsforreal-timesignalprocessingandcontrolapplicationsARMCortex-MSeries:Deeplyembeddedprocessorsoptimizedformicrocontrollerandlow-powerapplicationsCortex-MProcessorFamilySeamlessembeddedarchitectureSpanningcostandperformancepoints5Cortex-MProcessorSolutionEnergyefficiencyLowerenergycostsEaseofuseLowersoftwarecostsHighperformanceCompetitiveproductsReducedsystemcostLowersiliconcostsLowpowerimplementationSleepmodesupportWake-upInterruptControllerIncreasedintelligenceatnodeBroadtoolsandOSsupportBinarycompatibleroadmapPureCtarget32-bitRISCarchitectureHighefficiencyprocessorcoresIntegratedInterruptController(NVIC)Thumb-2codedensityAreaoptimiseddesignsCoreSightsupport6SpanningtheApplicationRangeForgettraditional8-/16-/32-bitclassificationsSeamlessarchitectureacrossallapplicationsCortex-M0Cortex-M3Cortex-M4“8/16-bit”applications“16/32-bit”applications“32-bit/DSP”applicationsUltra-lowpowerLowcostOptimisedconnectivityPerformanceefficiencyFeature-richconnectivityMCUplusDSPHighefficiencyAcceleratedSIMD,FP&DSP7AddressingProprietaryMCUSpaceCortex-M4Cortex-M3Cortex-M0RenesasH8FreescaleHCS08MicrochipPIC18TIMSP4308051AVR8InfineonC166Freescale58xxxMicrochipdsPICMicrochipPIC24RenesasSuperHAtmelAVR32TIC2000MicrochipPIC32TIMSP430AtmelAVR32InfineonC166RenesasSuperH8Cortex-MLicenseGrowth9EmbeddedShipmentbasedonARMUnit:Million10InstructionSetArchitectureSMLATTSMLALBBSADD16SMLABTPKHSADD8QADDSASXQADD16SELQADD8SHADD16QASXSHADD8QDADDSHASXQDSUBSHSAXQSAXSHSUB16QSUBSHSUB8QSUB16SMLABBQSUB8SMLADSMLALBTSMLATBSMLALDSMLAWTSMLALTBSMLAWBSMLSDSMLALTTSMMLSSMUADSMLSLDSMMULSMULBBSMMLASMULTTSMULWTSMULBTSMULWBSMUSDSMULTBSSUB16SXTABSSAT16SSUB8SXTAB16SSAXUADD16UASXSXTAHUADD8UHADD16SXTB16UHADD8UHASXUHSUB8UQADD16UHSAXUMAALUQADD8UHSUB16UQSUB16USAD8UQASXUQSUB8USADA8UQSAXUSAT16USAXUXTABUXTAHUSUB16UXTAB16UXTB16USUB8MERLINCORTEX-M3CORTEX-M0/M1ADCBLADDADRBBICCMNCMPEORLDMLDRLDRBLDRHLDRSHLSLLSRMOVMULMVNPOPPUSHRORSBCSTMSTRSTRBSTRHSUBLDRSBSVCTSTANDASRORRRSBITADCADDADRANDASRBBFCBFIBICCBNZCBZCLREXCLZCMNCMPDBGCDPEORLDCLDMIALDMDBLDRLDRBLDRBTLDRDLDREXLDREXBLDREXHLDRHLDRHTLDRSBLDRSBTLDRSHLDRSHTLDRTLSLLSRMCRMCRRMLAMLSMOVMOVTMRCMRRCMULMVNNOPORNORRPLDPLDWPLIPOPPUSHRBITREVREV16REVSHRORRRXRSBSBCSBFXSDIVSEVSMLALSMULLSSATSTCSTMIASTMDBSTRSTRBSTRBTSTRDSTREXSTREXBSTREXHSTRHSTRHTSTRTSUBSXTBSXTHTBBTBHTEQTSTUBFXUDIVUMLALUMULLUSATUXTBUXTHWFEWFIYIELDWFIYIELDBKPTBLXBXCPSDMBISBMRSMSRNOPREVREV16REVSHSEVSXTBSXTHUXTBUXTHWFEDSBVSUBVMOVVSTMVABSVMRSVADDVMSRVCMPVMULVCMPEVNEGVCVTVNMLAVCVTRVNMLSVDIVVNMULVLDMVPOPVLDRVPUSHVMLAVSQRTVMLSVSTRMERLIN-FP11NestedVectoredInterruptControllerFasterinterruptresponseWithlesssoftwareeffortISRwrittendirectlyinCPointertoCroutineatvectorISRisaCfunctionIntegratedNVIChandles:SavingcorruptibleregistersExceptionprioritizationExceptionnesting8051Cortex‐M1)SJMP/L JMP from vector table to handler2)PUSH PSW3)ORLPSW, #00001000b (to switch register bank)4)Starting real handler code1)Starting real handler code12UltraLowPowerARMCortex-MprocessorsoptimizedforlowpowerArchitectedsupportforsleepstatesandWICExcellentresultswithARMPhysicalIPUsingPMK,leakageisaslowas7nAleakageinstateretentionmodeCortex-M0sleepmodeleakage(nanowatts)0100200300400500600700180G180ULL180ULLPMK12xreduction50xreduction13ARMMCUInto“Sub1USD”Zone14Thesmallest,lowestpowerARMprocessorAthirdoftheareaandpowerofARM7TDMI-S™processor12Kgates,47μA/MHzon180ULLinminimalconfiguration*0.9DMIPS/MHzperformanceARMCortex-M0ProcessorSignificantadvantagesover8/16-bitLongerbatterylifethroughenergyefficiencyReducedsystemcostthroughcodedensityPerformanceheadroomforadvancedfeaturesExtendsARMarchitecturetonewapplicationsUltralow-powerMCUandmixed-signaldevicesIdealsequencerorFSMreplacementonSoCBinaryandtoolsupwardscompatiblewithCortex-M3processor15EfficiencywithµAtospareExtremelylowpowerleakageandoperation67µA/MHzactive,7nAstateretentioninfullconfiguration*ReducedFlashaccessandnospeculativefetchesSignificantenergyefficiencyadvantageover8/16-bitOver2-4xshorterdutycyclethanMSP430andPIC18**Workingsmarter,sleepinglongerIdealinpoweroptimizeddesigns*UsingARMPhysicalIPwithPMKon180ULLprocessat1.8V-ARMCortex-M0infullconfiguration(32interrupts,fastmul,debug)**Basedonbenchmarksinpublicdomain.D
本文标题:ARM Cortex-M MCU 准架构
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