verilog初学者-学习ppt

VerilogTutorialAndCodingStyleVerilogworkshopVerilogTutorialAndCodingStyleInstituteofArtificialIntelligenceandRobotics葛晨阳西安交大SOC设计中心VerilogworkshopVerilogCodingStyle推荐工具1.HDL设计规则检查器--nlint语法语义检查，增强代码的可读性、易维护和复用；涉及Simulation、Synthesis、DFT、CodingStyle2.HDL代码编辑工具--HDLTurboWriter功能很强大，专门用于编写HDL代码3.代码编辑工具--UltraEditor文本编辑工具，用于C/C++/Verilog/VHDL编程。4.仿真工具--ModelSim/Verilog-XLInstituteofArtificialIntelligenceandRoboticsVerilogworkshopTypicalICDesignFlowTypicalICDesignFlowInstituteofArtificialIntelligenceandRoboticsVerilogworkshopTypicalICDesignFlowSpecificationRTLcodingRTLsimulationSynthesisTiminganalysisGatelevelsimulationFPGAtestPlace&RouteLayoutparasiticsFinaltestTapeoutTypicalICDesignFlowInstituteofArtificialIntelligenceandRoboticsVerilogworkshopThat’scrazywork.Goodtoolsalways•RTL:VerilogVHDL•Simulation:NC-VerilogVCSDebussy•Synthesis:DesignCompiler•CodingStyle:nlint•FPGA:XilinxISE/AlteraQuartusII•P&R:SoCEncounter/Astroandmanymanymore……helpmuch!!!TypicalICDesignFlowInstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoVerilogIntroductiontoHDLInstituteofArtificialIntelligenceandRoboticsInstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoHDLVerilog发展历史Verilog-XL诞生Cadence购买Verilog版权VerilogHDL公开发表VerilogHDL移交OVIVerilogIEEE1364-1995标准公开发表VerilogIEEE1364-2001标准公开发表19801989199019952001InstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoHDLVerilog适用的设计•SystemAlgorithmic(算法)–thefunctionofthesystem•RTL–thedataflow(流程)–thecontrolsignals(控制信号)–thestorageelementandclock(存储单元与四周)•Gate–gate-levelnet-list•Switch–transistor-levelnet-listInstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoHDLngresetClkOut[3:0]counter_44-bitcounterdesignVerilogworkshop4-bitcounterdesignSchematicIntroductiontoHDLInstituteofArtificialIntelligenceandRoboticsVerilogworkshop4-bitcounterdesignHDL(Verilog)modulecounter_4(clk,ngreset,out);inputclk,ngreset;output[3:0]out;reg[3:0]out;always@(posedgeclkornegedgengreset)if(!ngreset)out=4’b0;elseout=#1out+1;endmoduleIntroductiontoHDLInstituteofArtificialIntelligenceandRoboticsVerilogworkshopHDLCodingbottomupcomplextimeconsumingspecifiedhardtounderstandVStopdownsimplelaborsavingstandardeasytounderstandSCHEMATICIntroductiontoHDLInstituteofArtificialIntelligenceandRoboticsVerilogworkshop练习1：编译Counter_4，写出testbench，观察波形使用modelsim仿真工具编译、仿真moduletb_counter_4;提示：定义clk，ngresetinitialbegin….end初始化clk，ngreset值#n延时n纳秒always＋#n延时产生clk时钟endmoduleIntroductiontoHDLInstituteofArtificialIntelligenceandRoboticsVerilogworkshop练习1：Testbenchforcounter_4moduletb_counter_4;regclk,ngreset;wire[3:0]out;initialbeginclk=1'b0;ngreset=1'b1;#10ngreset=1'b0;#20ngreset=1'b1;endalways#5clk=~clk;counter_4counter_inst(.clk(clk),.ngreset(ngreset),.out(out));endmoduleIntroductiontoHDLInstituteofArtificialIntelligenceandRoboticsVerilogworkshopVerilogBasicmodulemodule_name(port_list);Declarations:Input,outputandinoutdeclarations.Netdeclarations.Regdeclarations.Parameterdeclaration.Initialstatement.Gateinstantiationstatement.Moduleinstantiationstatement.UDPinstantiationstatement.Alwaysstatement.Continuousassignment.endmoduleInstituteofArtificialIntelligenceandRoboticsworkshopVerilogBasicVerilogAsimpleVerilogexample:shiftregisterdesignmoduleshift(data_out,data_in,rst_,clk);output[3:0]data_out;inputdata_in;inputrst_;inputclk;reg[3:0]data_out;wire[3:0]data_out_next;assigndata_out_next={data_out[2:0],data_in};always@(posedgeclkornegedgerst_)if(!rst_)data_out=4’b0;elsedata_out=#1data_out_next;endmodulemoduledeclarationoutputdeclarationinputdeclarationregisterdeclarationwiredeclarationCombinationallogicSequentiallogicin/outportsInstituteofArtificialIntelligenceandRoboticsVerilogworkshopVerilogBasic•moduledeclaration:definethemodulename•in/outportdeclaration:definethein/outportname•inputdeclaration:definetheinputportnameanditsbit-width•outputdeclaration:definetheoutputportnameanditsbit-width•registerdeclaration:definetheregisternameanditsbit-width•wiredeclaration:definethewirenameanditsbit-width•combinationallogic:describethecombinationallogicinyourdesign•sequentiallogic:describethesequentiallogicinyourdesignInstituteofArtificialIntelligenceandRoboticsVerilogworkshopVerilogBasicReg0Reg1Reg2Reg3data_inrst_clkdata_outTherealdesignresultInstituteofArtificialIntelligenceandRoboticsInstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoHDLModulemodulemodule_name(port_name);Definitions(Port,Wire,Register,Parameter,…)ModuleInstantiations(模块的例化)ModuleStatements&ConstructsEndmodule•模块中可以调用其他模块的別名，本身也可以被其他的模块所调用。InstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoHDL合法的字InstituteofArtificialIntelligenceandRoboticsVerilogworkshopIntroductiontoHDLModuleinstancesmodulefadder(a,b,cin,sum,cout);input[3:0]a,b;inputcin;output[3:0]sun;outputcout;//创造四个加法器的例化名，并输入一组信号fa32fa0(a[0],b[0],cin,sum[0],c1);fa32fa1(a[1],b[1],c1,sum[1],c2);fa32fa2(a[2],b[2],c2,sum[2],c3);fa32fa3(a[3],b[3],c3,sum[3],cout);endmodulemodulefa32(a,b,cin,sum,cout);inputa,b,cin;output